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| MC1741C Internally Compensated, High Performance Operational Amplifier The MC1741C was designed for use as a summing amplifier, integrator, or amplifier with operating characteristics as a function of the external feedback components. * No Frequency Compensation Required * Short Circuit Protection * Offset Voltage Null Capability * Wide Common Mode and Differential Voltage Ranges * Low Power Consumption * No Latch Up http://onsemi.com MARKING DIAGRAMS 8 PDIP-8 P1 SUFFIX CASE 626 1 1 8 8 1 SO-8 D SUFFIX CASE 751 1 A = Assembly Location WL, L = Wafer Lot YY, Y = Year WW, W = Work Week 1741C ALYW MC1741CP1 AWL YYWW 8 PIN CONNECTIONS Offset Null 1 2 3 4 8 7 N.C. VCC Output Offset Null Equivalent Circuit Schematic (1/4 of Circuit Shown) G 4.5 k 39 k 25 30 pF 7.5 k Output 50 Offset Null 1.0 k 50 k 1.0 k 5.0 k 50 k 50 VEE VCC Inv. Input Noninv. Input VEE + 6 5 Noninverting Input Inverting Input (Top View) ORDERING INFORMATION Device MC1741CD MC1741CDR2 MC1741CP1 Package SO-8 SO-8 PDIP-8 Shipping 98 Units/Rail 2500 Tape & Reel 50 Units/Rail (c) Semiconductor Components Industries, LLC, 2000 1 April, 2000 - Rev. 6 Publication Order Number: MC1741C/D MC1741C MAXIMUM RATINGS Rating Power Supply Voltage Input Differential Voltage Input Common Mode Voltage (Note 1.) Output Short Circuit Duration (Note 2.) Operating Ambient Temperature Range Storage Temperature Range Symbol VCC, VEE VID VICM tSC TA Tstg Value 18 30 15 Continuous 0 to +70 -55 to +125 Unit Vdc V V - C C 1. For supply voltages less than +15 V, the absolute maximum input voltage is equal to the supply voltage. 2. Supply voltage equal to or less than 15 V. ELECTRICAL CHARACTERISTICS (VCC = +15 V, VEE = -15 V, TA = 25C, unless otherwise noted.) Characteristic Input Offset Voltage (RS 10 k) Input Offset Current Input Bias Current Input Resistance Input Capacitance Offset Voltage Adjustment Range Common Mode Input Voltage Range Large Signal Voltage Gain (VO = 10 V, RL 2.0 k) Output Resistance Common Mode Rejection (RS 10 k) Supply Voltage Rejection (RS 10 k) Output Voltage Swing (RL 10 k) (RL 2.0 k) Output Short Circuit Current Supply Current Power Consumption Transient Response (Unity Gain, Noninverting) (VI = 20 mV, RL 2.0 k, CL 100 pF) Rise Time (VI = 20 mV, RL 2.0 k, CL 100 pF) Overshoot (VI = 10 V, RL 2.0 k, CL 100 pF) Slew Rate Symbol VIO IIO IIB ri Ci VIOR VICR AVOL ro CMR PSR VO Min - - - 0.3 - - 12 20 - 70 75 12 10 - - - - - - Typ 2.0 20 80 2.0 1.4 15 13 200 75 90 - 14 13 20 1.7 50 0.3 15 0.5 Max 6.0 200 500 - - - - - - - - - - - 2.8 85 - - - mA mA mW s % V/s Unit mV nA nA M pF mV V V/mV dB dB V ISC ID PC tTLH os SR ELECTRICAL CHARACTERISTICS (VCC = +15 V, VEE = -15 V, TA = Tlow to Thigh, unless otherwise noted.)* Characteristic Input Offset Voltage (RS 10 k) Input Offset Current (TA = 0 to +70C ) Input Bias Current (TA = 0 to +70C ) Supply Voltage Rejection (RS 10 k) Output Voltage Swing (RL 2.0 k) Large Signal Voltage Gain (RL 2.0 k, VO = 10 V) * Tlow = 0C Thigh = 70C Symbol VIO IIO IIB PSR VO AVOL Min - - - 75 10 15 Typ - - - - 13 - Max 7.5 300 800 - - - Unit mV nA nA dB V V/mV http://onsemi.com 2 MC1741C 1000 en, INPUT NOISE ( Vpk) en, INPUT NOISE ( Vpk) BW = 1.0 Hz to 1.0 kHz 100 100 10 BW = 1.0 Hz to 1.0 kHz 10 1.0 0 10 100 1.0 k 10 k RS, SOURCE RESISTANCE () 100 k 1.0 M 0.1 10 100 1.0 10 k 100 k RS, SOURCE RESISTANCE () 1.0 M Figure 1. Burst Noise versus Source Resistance Figure 2. RMS Noise versus Source Resistance 10 en, OUTPUT NOISE (mVrms) AV = 1000 1.0 100 10 0.1 1.0 0.01 10 100 1.0 k 10 k 100 k 1.0 M e n, INPUT NOISE ( nV/ Hz ) 14.0 12.0 10.0 8.0 6.0 4.0 2.0 0 10 100 1.0 k f, FREQUENCY (Hz) 10 k 100 k AV = 10, RS = 100 k RS, SOURCE RESISTANCE () Figure 3. Output Noise versus Source Resistance Figure 4. Spectral Noise Density 100 k Positive Threshold Voltage + x500 x2 Low Pass Filter 1.0 Hz to 1.0 kHz Negative Threshold Voltage + To Pass / Fail Indicator + - 100 k 1.0 k 100 k Operational Amplifier Under Test Unlike conventional peak reading or RMS meters, this system was especially designed to provide the quick response time essential to burst (popcorn) noise testing. The test time employed is 10 sec and the 20 mV peak limit refers to the operational amplifier input thus eliminating errors in the closed loop gain factor of the operational amplifier. Figure 5. Burst Noise Test Circuit http://onsemi.com 3 MC1741C 28 VO, OUTPUT VOLTAGE (Vpp ) 24 Avol , VOLTAGE GAIN (dB) 20 16 12 8.0 4.0 0 10 100 1.0 k f, FREQUENCY (Hz) 10 k 100 k (Voltage Follower) THD < 5% 120 100 80 60 40 20 0 -20 1.0 10 100 1.0 k 10 k 100 k 1.0 M 10 M f, FREQUENCY (Hz) Figure 6. Power Bandwidth (Large Signal Swing versus Frequency) Figure 7. Open Loop Frequency Response 15 VO, OUTPUT VOLTAGE (Vpp ) VO, OUTPUT VOLTAGE (Vpp ) 13 11 9.0 7.0 5.0 3.0 1.0 100 200 500 700 1.0 k 2.0 k 9.0 V 6.0 V 15 V Supplies 12 V -15 -13 -11 -9.0 -7.0 -5.0 -3.0 -1.0 100 200 500 700 1.0 k 2.0 k 12 V 9.0 V 6.0 V 5.0 k 7.0 k 10 15 V Supplies 5.0 k 7.0 k 10 k RL, LOAD RESISTANCE () RL, LOAD RESISTANCE () Figure 8. Positive Output Voltage Swing versus Load Resistance Figure 9. Negative Output Voltage Swing versus Load Resistance 28 26 24 22 20 18 16 14 12 10 8.0 6.0 4.0 2.0 0 VO, OUTPUT VOLTAGE SWING (Vpp ) 30 V Supply 27 V 24 V 21 V 18 V 15 V 12 V 9.0 V 6.0 V 5.0 V 1.0 2.0 Vin 200 k 50 k 50 k 3.0 4.0 5.0 6.0 7.0 RL, LOAD RESISTANCE (k) 8.0 9.0 10 200 k 3 2 100 F 1.0 k 10 k VCC + 7 MC1741 100 F RL 0 4 Figure 10. Output Voltage Swing versus Load Resistance (Single Supply Operation) Figure 11. Single Supply Inverting Amplifier http://onsemi.com 4 MC1741C 5.0 V/DIV Output Input 10 s/DIV Figure 12. Noninverting Pulse Response To Scope (Input) + RL CL To Scope (Output) Figure 13. Transient Response Test Circuit 105 100 AV, VOLTAGE GAIN (dB) 95 90 85 80 75 70 0 2.0 4.0 6.0 8.0 10 12 14 16 VCC, |VEE|, SUPPLY VOLTAGES (V) 18 20 Figure 14. Open Loop Voltage Gain versus Supply Voltage http://onsemi.com 5 MC1741C PACKAGE DIMENSIONS PDIP-8 P1 SUFFIX CASE 626-05 ISSUE K NOTES: 1. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 2. PACKAGE CONTOUR OPTIONAL (ROUND OR SQUARE CORNERS). 3. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. DIM A B C D F G H J K L M N MILLIMETERS MIN MAX 9.40 10.16 6.10 6.60 3.94 4.45 0.38 0.51 1.02 1.78 2.54 BSC 0.76 1.27 0.20 0.30 2.92 3.43 7.62 BSC --10_ 0.76 1.01 INCHES MIN MAX 0.370 0.400 0.240 0.260 0.155 0.175 0.015 0.020 0.040 0.070 0.100 BSC 0.030 0.050 0.008 0.012 0.115 0.135 0.300 BSC --10_ 0.030 0.040 8 5 -B- 1 4 F NOTE 2 -A- L C -T- SEATING PLANE J N D K M M TA M H G 0.13 (0.005) B M SO-8 D SUFFIX CASE 751-06 ISSUE T NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. DIMENSIONS ARE IN MILLIMETER. 3. DIMENSION D AND E DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE. 5. DIMENSION B DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 TOTAL IN EXCESS OF THE B DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM A A1 B C D E e H h L q MILLIMETERS MIN MAX 1.35 1.75 0.10 0.25 0.35 0.49 0.19 0.25 4.80 5.00 3.80 4.00 1.27 BSC 5.80 6.20 0.25 0.50 0.40 1.25 0_ 7_ A 8 D 5 C E H 1 4 0.25 M B M h B C e A SEATING PLANE X 45 _ q 0.10 A1 B 0.25 M L CB S A S http://onsemi.com 6 MC1741C Notes http://onsemi.com 7 MC1741C ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. PUBLICATION ORDERING INFORMATION NORTH AMERICA Literature Fulfillment: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada Email: ONlit@hibbertco.com Fax Response Line: 303-675-2167 or 800-344-3810 Toll Free USA/Canada N. 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